Successive cancellation decoding of polar codes using new hybrid processing element

Polar codes are one of the best linear block that capacity achieving and incorporating along with it a simplified encoding decoding routines. Successive cancellation (SC) algorithm is predominantly used algorithms due to its low complexity. It has broad scopes for hardware architecture design reformulation. For polar code, trade-off among long latency silicon area SC bottleneck high throughput decoder. The available prior decoder designs have higher requirements length. This paper introduces unique reformulation processing element (PE) decoding. proposed leads two benefits: firstly, critical path complexity PE meaningfully reduced by using unified adder block. Secondly, requirement power consumption were also considerably without any loss in performance. build various lengths. Moreover, Gate-level analysis revealed attains an 18% reduction 38% over conventional similar